Select ⚡ RC Path to open Elmore HUD
⚡ 3D Interconnect Extraction:
Net 1: Local (inv→nand2)
Net 2: Inter-Row (dfxtp→a21oi)
Net 3: Highway (buf→dfxtp)
Driver: sky130_fd_sc_hd__inv_2 (Rd=450Ω) → Load: sky130_fd_sc_hd__nand2_1 (Cin=2.4fF)
Manhattan Length: 34.2 µm
Wire R: 24.5 Ω
Wire C: 6.15 fF
Vias: 4 cuts (27.6 Ω)
Elmore τ: 6.42 ps
t_pd (50%): 4.45 ps
Slew (10→90%): 14.1 ps
🔬 Wafer Prep
Wafer Prep
Master
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Cause —
When (phase) —
Key params —
Pitfalls —
Interview hook —
Antenna Ratio = Metal Area (or perimeter) / Gate Oxide Area
📦 Wirebond Leadframe
Beginner
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L (typ) ~1.2 nH loop
Pitch ~75–100 µm pad
I/O dens. Low (perimeter)
Cost Low
Best for MCUs, QFN/SOIC
Illustrative leadframe + Au wires. Package delay is R+L / SSO — not on-die Elmore RC.
💎 ~2nm GAA + BSPD
Lowest advanced
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Device GAA nanosheet
BEOL Cu + EUV / multi-pattern
Power BSPD / PowerVia class
Key challenge Frontside track starvation + IR
Educational schematic — not a foundry DRC deck.
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P-type monocrystalline silicon bulk wafer. Shallow trench isolation (STI) etched with thermal oxide liner to isolate standard cells. Ion-implanted N-Wells and P-Wells form the active silicon foundation.